1. Field of the Invention
The present invention relates to a high breakdown voltage semiconductor device using dielectric isolation.
2. Description of the Related Art
In high breakdown voltage semiconductor devices, a dielectric isolation method is known as an effective method of isolating each element.
FIG. 1 shows a conventional high voltage diode obtained by using such a dielectric isolation method.
Referring to FIG. 1, a Si wafer is obtained by bonding p.sup.+ -or n.sup.+ -Si substrate 1a and n.sup.- -Si substrate 1b by a direct bonding technique; 3, a bonding interface, and 2, oxide film formed on bonding interface 3. Part of n.sup.- -Si substrate 1b of the Si wafer is etched to a depth reaching bonding interface 3 to form a groove, thereby forming island-like n.sup.- -layer 4. Oxide film 5 is formed on an inner surface of the groove, and polycrystalline Si film 6 is buried therein. P.sup.30 -layer 8 is formed in a central surface portion n.sup.- -layer 4, which has been isolated from other regions by oxide films 2 and 5, and p.sup.- -layer 9 is formed around p.sup.+ -layer 8, thereby constituting a diode. Furthermore, n.sup.+ -layer 10 is formed in a peripheral surface portion of n.sup.- -layer 4 so as to form an anode electrode.
In the diode described above, when a reverse bias is applied between the anode and cathode, a depletion layer extends from p.sup.+ -layer 8 into n.sup.- -layer 4. If the reverse bias is increased, a depletion layer extends from n.sup.+ -layer and reaches oxide film 2 formed on the bottom of n.sup.- -layer 4. The depletion layer cannot extend any longer. Since the potential at substrate 1a is normally set at 0 V, the voltage between the anode and cathode is applied to the depletion layer generated in N.sup.- -layer 4 and oxide film 2. However, since oxide film 2 is considerably thin and has a high dielectric constant, most of the voltage is applied to the depletion layer. Therefore, in order to sufficiently increase the breakdown voltage of the diode, the thickness of n.sup.- -layer 4 must be sufficiently increased. However, if the thickness of n.sup.- -layer 4 is increased, the depth of the groove for element isolation must be increased accordingly. This makes it difficult to perform dielectric isolation, especially, in a lateral direction. In addition, if p.sup.- -layer 9 formed on the surface is not depleted at the same time when n.sup.- -layer 4 is completely depleted, punch-through can be easily caused between p.sup.- - and n.sup.+ -layers 9 and 10.
In addition, a large amount of crystal defects appear which are arranged the grooves. Thus, when transistors are formed in the isolated layer 4, however, many recombinations are caused and life times of carriers are shortened, and therefore, current gain is lowered.
As described above, in a semiconductor element having the conventional dielectric isolation structure, the thickness of a high-resistance semiconductor layer must be sufficiently increased to obtain a sufficiently high breakdown voltage. However, such an arrangement makes it difficult to perform element isolation from the technical viewpoint.